The present invention relates to the field of test and verification of a new digital system combining software and processor hardware. In particular, the present invention relates to a method and system for verifying the correctness of the system behavior of a processor cooperating with software.
In the following, the expression xe2x80x9ccentral processing unitxe2x80x9d (CPU) refers to a portion of a computer that controls all the other parts and provides an architectural interface for application programs running on the computer. The expression xe2x80x9cprocessorxe2x80x9d refers to a portion of the CPU that is implemented in hardware and comprises a control unit, i.e., a part of the processor responsible for performing the machine cycle comprising the steps of fetching, decoding, executing, storing, an arithmetic and logic unit (ALU) and memory, such as registers, cache, RAM (Random Access Memory) and ROM (Read-Only Memory) as well as various temporary buffers and other logic.
The expression xe2x80x9cmicrocodexe2x80x9d denotes a technique for implementing the instruction set of a CPU as a sequence of microcode instructions, also called xe2x80x9cmicroinstructionsxe2x80x9d. In contrast, the instruction set of the CPU is also called xe2x80x9cmacroinstrutionsxe2x80x9d or xe2x80x9cmachine languagexe2x80x9d and actually defines the architectural interface of the CPU.
Each of the microinstructions typically consists of a large number of bit fields and the address of the next microinstruction to execute. Each bit field controls some specific part of the processor""s operation, such as a gate which allows some functional unit to drive a value onto the bus or the operation to be performed by the ALU (Arithmetic and Logic Unit). A functional unit is basically a subsystem of the central processing unit of a computer, and the bus is basically one of the sets of conductors, e.g., wires or connections in an integrated circuit, connecting the various functional units in a processor and computer respectively.
Several microinstructions will usually be required to fetch, decode and execute each machine language instruction, also referred to as xe2x80x9cmacroinstructionxe2x80x9d. The microcode may also be responsible for polling for hardware interrupts between each macroinstruction, e.g., checking the status of an input line, sensor, or memory location to see if a particular external event has been registered. Writing microcode is known as xe2x80x9cmicroprogrammingxe2x80x9d.
During the development process of a newly designed processor, it is necessary to perform several verification steps, to determine whether or not the processor or parts of it fulfill a set of established requirements depending on a given phase in its life-cycle. The development process is completed by tests which typically include unit tests, integration tests and finally a system test.
In the development of a CPU implemented with microcode, both the microcode and the processor hardware need to be tested. Since the microcode and the processor hardware are tied together very closely it is hardly possible to test or verify the microcode and the processor hardware thoroughly without having both interact with each other. In current development and test procedures the microcode and the processor hardware are combined for the first time when the processor hardware becomes available, i.e., when the processor or at least a prototype of it has been manufactured. At this point, an integration process starts including testing, modification of the microcode, re-testing and so on, until the developers and testers are satisfied with the results. Up to the start of the integration process the microcode and the processor hardware are tested in heterogeneous, incompatible test and simulation environments. Both can be tested in only rudimentary ways.
In order to speed up the overall development process, there is a need for a method and system for eliminating architectural errors and verifying proper microcode operation as early in the design stage as possible in order to avoid propagation of early development errors.
U.S. Pat. No. 4,520,440 discloses a method of testing the hardware and the microcode associated with a processor under test having a limited instruction set. According to that patent, a minimum test driver, under control of a test processor, loads the data necessary to execute the instruction being tested. After execution of the instruction, the test driver directs capture of the execution results for appropriate use. As an aid in performing the verification test, the test driver is provided with an invalid command that forces return of control to the test processor. The test driver is loaded and run under control of the support processor which provides actual or simulated I/O capabilities. In operation, the processor to be microcoded is tested instruction by instruction, via shared memory, with microcode corrections being made on the same basis to avoid error propagation.
The aforementioned method of testing the processor hardware and the microcode enables the test crew to start testing the microcode together with the associated processor hardware in an earlier stage, before the complete functionality has been implemented in the processor hardware. However, a test or verification that covers all the functionality of the microcode and the processor hardware can still be started only when all the components of the processor hardware are available.
It is therefore an object of the present invention to provide a method and a system that allows a full integrated verification of software and processor hardware comparable early in the design stage.
The foregoing object is achieved by a method and a system for verifying a processor cooperating with software according to claim 1. The software can be any kind of computer program interacting with the processor, such as basic routines used to start or stop the processor or microcode. Advantageously, the inventive method can be used to verify the correctness of the system behavior of a processor having at least a part of its instructions implemented with microcode. First, the software or microcode is independently tested by using a functional emulator performing in the same way as the hardware of said processor according to the processor""s functional specification. Then, the software or microcode is tested by using a hardware emulator behaving in the same way as said hardware of said processor according to the design of said processor""s logic gates. Finally, the software or microcode is tested against the actual hardware.
In a preferred embodiment, the method is suitable for verifying a processor implemented with microcode consisting of different kinds of microcode that have to be tested differently. The method further comprises the step of testing the different kinds of microcode separately by using simulators behaving like the functional specification of the hardware on which the different kinds of code are expected to run. Only after completion of such tests are the different kinds of microcode combined and tested together, still using a simulation environment.
The present invention also provides a system for verifying the architectural correctness of a CPU having at least a part of its instruction set implemented with microcode. It can be used for testing microcode that includes different kinds of microcode, namely, millicode procedures and processor code functions. The system comprises a functional emulator performing in the same way as the hardware of the processor according to the processor""s functional specification for testing the millicode, a simulator controlling a virtual machine providing a platform for testing the processor code functions, and a hardware emulator behaving in the same way as the hardware of the processor according to the design of the processor""s logic gates for testing the microcode.